We introduce a 16 × cascaded time difference amplifier (TDA) using a differential logic delay cell with 0.18 µm CMOS process. By employing the differential logic delay cell in the delay chain instead of the CMOS logic delay cell, less than 8% TD gain offset with 150 ps input range is achieved. The input referred standard deviation of the output time difference error is 2.7 ps and the input referred is improved by 17% compared with that of the previous TDA using the CMOS logic delay cell.

This paper demonstrates the resonant power supply noise reduction effects of STO thin film decoupling capacitors, which are embedded in interposers. The on-interposer STO capacitor consists of SrTiO2 whose dielectric constant is about 20 and is sandwitched by Cu films in an interposer. The on-interposer STO capacitors are directly connected to the LSI PADs so that they provide large decoupling capacitance without package leadframe/bonding wire inductance, resulting in the reduction of the resonant power supply noise. The measured power supply waveforms show significant reduction of the power supply noise, and the Shmoo plots also show the contribution of the STO capacitors to the robust operations of LSIs.

This paper demonstrates a quick start method for Pulse-Width Controlled PLL (PWPLL). Our PLL converts the internal state into digital signals and stores them into a memory before getting into a sleep mode. The wakeup sequence reads the memory and presets the internal state so that our PLL can start the operation with close to the previously locked condition. Since the internal state includes not only the frequency control code but also the phase information, our quick start PLL locks in several clock cycles. A prototype chip fabricated in 0.18µm standard CMOS shows 50ns settling time (4 reference clock cycles), 18.5mW power consumption under 1.8V nominal supply voltage with 105µm×870µm silicon area.

In this paper, we propose a novel gate delay time mismatch tolerant time-mode signal accumulator whose input and output are represented by a time difference of two digital signal transitions. Within the proposed accumulator, the accumulated value is stored as the time difference between the two pulses running around the same ring of a delay line, so that there is no mismatch between the periods of the two pulses, thus the output drift of the accumulator is suppressed in principle without calibrating mismatch of two rings, which is used to store the accumulated value in the conventional one. A prototype of the proposed accumulator was fabricated in 180nm CMOS. The accumulating operation is confirmed by both time and frequency domain experiments. The standard deviation of the error of the accumulating operation is 9.8ps, and compared with the previous work, the peak error over full-scale is reduced by 46% without calibrating the output drift.

This paper proposes a time-to-digital converter (TDC) utilizing the cascaded time difference amplifier (TDA) and shows measurement results with 0.18 µm CMOS. The proposed TDC operates in two modes, a wide input range mode and a fine time resolution mode. We employ a non-linearity calibration technique based on a lookup table. The wide input range mode shows 10.2 ps time resolution over 1.3 ns input range with DNL and INL of +0.8/-0.7LSB and +0.8/-0.4LSB, respectively. The fine time resolution mode shows 1.0 ps time resolution over 60 ps input range with DNL and INL of +0.9/-0.9LSB and +0.8/-1.0LSB, respectively.

This paper proposes a triangular active charge injection method to reduce resonant power supply noise by injecting the adequate amount of charge into the supply line of the LSI in response to the current consumption of the core circuit. The proposed circuit is composed of three key components, a voltage drop detector, an injection controller circuit and a canceling capacitor circuit. In addition to the theoretical analysis of the proposed method, the measurement results indicate that our proposed method with active capacitor can realize about 14% noise reduction compared with the original noise amplitude. The proposed circuit consumes 25.2 mW in steady state and occupies 0.182 mm2.

This paper demonstrates an autonomous di/dt control of power supply for margin aware operation. A di/dt on the power line is detected by a mutual inductor, the induced voltage is multiplied by Gilbert multiplier and the following low pass filter outputs a DC voltage in proportion to the di/dt. The DC voltage is compared with reference voltages, and the modes of the internal circuit is controlled depending on the comparators output. By using this scheme, the di/dt noise power can be autonomously controlled to fall within a defined range set by the reference voltages. Our experimental results show that the internal circuit oscillates between the all-active and the half-active modes, also show that the all/half ratio and the oscillation frequency changes depending on the reference voltages. It proves that our autonomous di/dt noise control scheme works as being designed.

We propose an open source cell library characterizer. Recently, free and open-sourced silicon design communities are attracted by hobby designers, academies and industries. These open-sourced silicon designs are supported by free and open sourced EDAs, however, in our knowledge, tool-chain lacks cell library characterizer to use original standard cells into digital circuit design. This paper proposes an open source cell library characterizer which can generate timing models and power models of standard cell library.